收藏本站
LHF32KZM
19
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations With WP#=V IH ,
individual block lock-bits can be set using the Set
Block Lock-Bit command. See Table 13 for a
summary of hardware and software write protection
options.
Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 12). The CPU can detect the completion
of the set block lock-bit event by analyzing the STS
pin output or status register bit SR.7.
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur
only when V CC =V CC1/2 and V PP =V PPH1/2/3 . In the
absence of this high voltage, block lock-bit contents
are protected against alteration.
A successful set block lock-bit operation requires
WP#=V IH . If it is attempted with WP#=V IL , SR.1 and
SR.4 will be set to "1" and the operation will fail. Set
block lock-bit operations with WP#<V IH produce
spurious results and should not be attempted.
block lock-bits can be cleared using only the Clear
Block Lock-Bits command. See Table 13 for a
summary of hardware and software write protection
options.
Clear block lock-bits operation is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 13). The CPU can detect
completion of the clear block lock-bits event by
analyzing the STS Pin output or status register bit
SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when
V CC =V CC1/2 and V PP =V PPH1/2/3 . If a clear block lock-
bits operation is attempted while V PP ≤ V PPLK , SR.3
and SR.5 will be set to "1". In the absence of this high
voltage, the block lock-bits content are protected
against alteration. A successful clear block lock-bits
operation requires WP#=V IH . If it is attempted with
WP#=V IL , SR.1 and SR.5 will be set to "1" and the
operation will fail. Clear block lock-bits operations
with V IH <RP# produce spurious results and should
not be attempted.
If a clear block lock-bits operation is aborted due to
V PP or V CC transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
4.13 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP#=V IH ,
Rev. 1.6
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
LH28F320SKTD-ZR IC FLASH 32MBIT 70NS 48TSOP
LHF00L28 IC FLASH 16MBIT 70NS 48TSOP
LPM409 CHASSIS STNRD 4SLOT CHASSIS W/INPUT LEAD
LS15RB1201J04 POE SPLITTER 10.8W 12V @0.9A
LT1932ES6#TRMPBF IC LED DRIVR WHITE BCKLGT TSOT-6
LT1937ES5#TRMPBF IC LED DRIVR WHITE BCKLGT TSOT-5
LT3003EMSE#TRPBF IC LED DRIVER BALLASTER 10-MSOP
LT3465AES6#TRMPBF IC LED DRIVR WHITE BCKLGT TSOT-6
相关代理商/技术参数
LH28F320S3-L11 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:32-MBIT(4MBx8/2MBx16)Smart 3 Flash MEMORY
LH28F320S3-L110 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:32-MBIT(4MBx8/2MBx16)Smart 3 Flash MEMORY
LH28F320S3-L130 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:32-MBIT(4MBx8/2MBx16)Smart 3 Flash MEMORY
LH28F320S3-L14 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:32-MBIT(4MBx8/2MBx16)Smart 3 Flash MEMORY
LH28F320S3-L140 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:32-MBIT(4MBx8/2MBx16)Smart 3 Flash MEMORY
LH28F320S3-L160 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:32-MBIT(4MBx8/2MBx16)Smart 3 Flash MEMORY
LH28F320S3NS 制造商:SHARP 制造商全称:Sharp Electrionic Components 功能描述:Smart voltage 32Mbit Flash Memory
LH28F320S3NS-L11 功能描述:IC FLASH 32MBIT 110NS 56SSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:60 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 线串行 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1449 (CN2011-ZH PDF)